최신ARM Accredited engineer - EN0-001무료샘플문제
When should an ISB instruction be used?
A message passing system between two CPUs is implemented using data stored in a shared area of memory. To pass a message, the first CPU executes the instructions:

The second CPU receives the message using the instructions:

On both CPUs, r1 = 0x5000 and r2 = 0x6000. At which of the points A, B, C and D must Data Memory Barrier (DMB) instructions be placed in order to ensure messages are passed reliably and efficiently?
Which of the following pairs of statements about the difference between a Memory Management Unit (MMU) and a Memory Protection Unit (MPU) is correct?
When developing a product using the standard ARM C library, what is the minimum effort required to re-target all platform-specific functions in the library?
In which of these cases would code have better performance when compiled for Thumb state than when compiled for ARM state?
In an ARMv7-R processor, with which level of the memory system is the Memory Protection Unit (MPU) associated?
A simple method of measuring the performance of an application is to record the execution time using the clock on the wall or a wristwatch.
When is this method INAPPROPRIATE?
To return from a Data Abort handler and re-execute the aborting instruction, what value should be loaded to the PC?
An ARM Cortex-A9 multi-core system has two CPUs, C1 and C2, each with a corresponding data cache. The code running on C1 writes to a memory location M.
and C1 updates its data cache, but not main memory. After that, C2 tries to read the contents of memory location M.
Which of the following hardware can automatically (without software inteivention) ensure that C2 reads the updated contents of M?
Is it possible to use an interrupt controller based on the Generic Interrupt Controller (GIC) architecture in a device built around a single core Cortex-A9 MPCore processor?
An ARMv7 implementation might include the VFPv4-D32 floating point extension. What does the '32' indicate?